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Altera_Forum's avatar
Altera_Forum
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16 years ago

New to VHDL: Understanding timer.vhd implementation

I'm an old hand at C/C++ just getting my feet wet with VHDL. In the course of my learning, I've used the SOPC builder to create a simplified system that included a timer. Part of the emitted VHDL c...
Altera_Forum's avatar
Altera_Forum
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15 years ago

The code snippets I've been listing are from the VHDL code that was emitted (automatically generated) as a result of including a timer using the SOPC builder. In other words, I'm including it from Library > Peripherals > Microcontroller Peripherals > Interval Timer, generating the system, and then looking at the result as a point of reference as I delve into VHDL.

It's *that* code that is including the extra std_logic'() stuff as well as including what looks like the vacuous use of an internal signal (clk_en).

--tim