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Honored Contributor
Honored ContributorNew to VHDL: Understanding timer.vhd implementation
I'm an old hand at C/C++ just getting my feet wet with VHDL. In the course of my learning, I've used the SOPC builder to create a simplified system that included a timer. Part of the emitted VHDL c...
Altera_ForumHonored Contributor
Honored ContributorI concur with josyb. It can be quite tricky at first trying to work out why a signal is changing on a clock but not acted upon until the next clock, which is why making inputs change on the falling edge can make thing a little clearer. This way they are only ever active for 1 clock edge, not 2 like you previously thought.
