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Honored Contributor
Honored ContributorNew to VHDL: Understanding timer.vhd implementation
I'm an old hand at C/C++ just getting my feet wet with VHDL. In the course of my learning, I've used the SOPC builder to create a simplified system that included a timer. Part of the emitted VHDL c...
Altera_ForumHonored Contributor
Honored ContributorYour line of thought is quite correct. If you change the input signals at the same time as clk rising, that very rising edge of the clk sees the previous values and it is only at the next rising edge of clk that the input changes will be evaluated.
I assume you are doing a functional simulation. In that case you could change the inputs at the falling edge of the clock (or at one quarter after the rising edge). Now the next rising edge will nicely evaluate all changes in one action. In real life your MM Slave will not require a wait-cycle, because the changes will be the effect of a (previously) rising clock edge.
