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Altera_Forum
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9 years ago

new to NIOS II. Need help for my requirement.

I am using Altera Arria V GX FPGA, 5AGXMA5G4F35C5N. I would like to run NIOS soft core in this FPGA.

I would like to have Ethernet 100MB and M.2 PCIe x 4 interfaces. I am hardware engineer hence I have no knowledge of NIOS, hence your inputs highly appreciated.

Does NIOS II support Ethernet 100MB and M.2 PCIe x 4 interfaces? What is the maximum ethernet speed I can achieve?

Is it possible to implement both MAC & PHY inside FPGA using NIOS?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    See Altera's "triple-speed ethernet megacore function user guide (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_ethernet.pdf)". This supports 10/100/1000-Mbps Ethernet. Note - this IP requires a license. This will give you the MAC but not the Phy. You'll need an external device to implement the Phy.

    M.2 PCIe x 4? Arria V FPGAs support PCIe Gen2 x4 if that's what you mean. Refer to the "arria v avalon-mm interface for pcie solutions user guide (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_a5_pcie_avmm.pdf)" for full details.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Hi,

    can any body help me.

    i'm working with altera university program DE4 board, i'm using NIOS II to commande the transfer of data from FPGA to My SD_Card.

    While building my projet within Eclipse this error appear.

    need your help!!

    Info: Linking TestSD.elf

    nios2-elf-g++ -T'../TestSD_bsp//linker.x' -msys-crt0='../TestSD_bsp//obj/HAL/src/crt0.o' -msys-lib=hal_bsp -L../TestSD_bsp/ -Wl,-Map=TestSD.map -O0 -g -Wall -mno-hw-div -mhw-mul -mhw-mulx -mgpopt=global -o TestSD.elf obj/default/hello_world.o -lm -msys-lib=m

    c:/intelfpga/17.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/bin/ld.exe: TestSD.elf section `.text' will not fit in region `onchip_memory2_0'

    c:/intelfpga/17.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/bin/ld.exe: address 0x1d92c of TestSD.elf section `.rwdata' is not within region `onchip_memory2_0'

    c:/intelfpga/17.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/bin/ld.exe: address 0x1fd48 of TestSD.elf section `.bss' is not within region `onchip_memory2_0'

    c:/intelfpga/17.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/bin/ld.exe: address 0x1d92c of TestSD.elf section `.rwdata' is not within region `onchip_memory2_0'

    c:/intelfpga/17.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/bin/ld.exe: address 0x1fd48 of TestSD.elf section `.bss' is not within region `onchip_memory2_0'

    c:/intelfpga/17.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/bin/ld.exe: region `onchip_memory2_0' overflowed by 93512 bytes

    collect2.exe: error: ld returned 1 exit status

    make: *** [TestSD.elf] Error 1