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Altera_Forum
Honored Contributor
Honored ContributorNew to FPGA - Question...?
Hello, I am new to Altera, FPGA and Verilog, however do have expirience programming TI TMS DSPs. How would you recommend starting the following basic design: I am looking to read ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- im just wondering is this the general workflow for professional designers --- Quote End --- It's a possible way to do it. At least some designers prefer schematic entry for the top level, others (me to) a pure HDL (VHDL or Verilog) design. I think, the addressed functionality (counters, registers, timers) can be easily implemented as behavioral HDL.
