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Altera_Forum
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11 years ago

New technique for pulse-width function on FPGAs

Hey all, I am beginning to write a paper on a new technique for making pulse-width generators on FPGAs and I was hoping I could get some help connecting it to the current state-of-the-art and g...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

FPGA vendors do not recommend internal clock generation apart from those out of PLL/DLL.

FPGA delays are not reliable and change per PVT and routing changes per compilation. Though such delays can be used for coarse delay dependant applications.

Your idea should suit ASIC