New technique for pulse-width function on FPGAs

I agree that temp., voltage, etc. can affect the timing of performing logic operations through the LUTs. Right now, my technique is just a proof-of-concept. I have developed the theory for why it should work and used the FPGA as a platform to test it. Ultimately, an ASIC could be created (with much more control over these parameters) for each pulse-width function that is desired.

Also, as far at the place and route, I can control these, in addition to the paths through the individual LUTs. However, these factors only lead to small discontinuities in the function f(w_{in}) = w_{out}, and the global function retains its shape even if I let the optimizer do its thing.

I guess I am asking, what could this be used for? What is similar that is out there?

Right now, the only types of pulse-width control circuits that I know of seem to be limited by the clock or some other on-board oscillator.

Thanks!