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Altera_Forum
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11 years ago

New technique for pulse-width function on FPGAs

Hey all, I am beginning to write a paper on a new technique for making pulse-width generators on FPGAs and I was hoping I could get some help connecting it to the current state-of-the-art and g...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

The problem with anything asynchronous on an FPGA is that the delay is affected by many things: Process, voltage, temperature and Place and Route.

You can lock down the P&R yourself, but you have no control over the other three.

How will your circuit overcome these delay/timing issues?