Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorNew technique for pulse-width function on FPGAs
Hey all, I am beginning to write a paper on a new technique for making pulse-width generators on FPGAs and I was hoping I could get some help connecting it to the current state-of-the-art and g...
Altera_ForumHonored Contributor
Honored ContributorThe problem with anything asynchronous on an FPGA is that the delay is affected by many things: Process, voltage, temperature and Place and Route.
You can lock down the P&R yourself, but you have no control over the other three. How will your circuit overcome these delay/timing issues?
