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Hi I am using the SOPC builder to create a NIOS based system. I wanted to use an open source tool minSSTA to perform timing analysis. The tool accepts .bench: circuit netlist file
- Here is a brief description of format of .bench file: ( from the tools readme file )
It starts by declaring the primary inputs/outputs. As an example,
INPUT(G0) -- 'G0' is a primary input (PI)
OUTPUT(G17) -- the output of gate 'G17' is a primary output (PO).
Since the PO name is not explicitly given, in MinnSSTA, the POs
are named after the gate providing the signal, e.g., POG17.
The netlist is described by a set of equation-like descriptions. For example,
G10 = NOR(G14, G11)
means that G10 is of NOR-type, and it has 2 inputs which are outputs of G14 and
G11, respectively.
So my question is can i get gate level netlist from the quartus tool in any format. I can write a script to convert it
Also I am not able to view the nios cpu in rtl viewer, so if use it in my design will i atleast be able to see its gate level netlist.
Thanks
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Hi,
you can choose under EDA tool setting -> Timing Analysis -> custom.
Quartus writes out a gatelevel netlist and a SDO file. The sdo file contains the timing information. The required libraries for the altera elements can be found under:
<Quartus install Dir>\quartus\eda\synthesis.
Kind regards
GPK
Honored Contributor
