Nest if statement in case statement

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Tnx for quick response.

The "No it is not" answer refers to customary or synthesizable or both of them?

Tnx

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unfortunately I disgree with the "no..." from fpga_guru011.

The main differences are to do with priority issues. the case statement is equivalent to multiple parallel ifs.

Most of everyday code is made up of " if" or "case" inside each other.

if rising_edge(clk) then

if enable = '1' then

case ....

when ....

if...

end if;

end case;

end if;

end if;