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Honored Contributor
Honored Contributornegative clock skews
Hi guys, Having a negative clock skew at the output registers of around -5ns when working at 225Mhz. One reason maybe that i am not assigning the clock pin to a dedicated clock pin in FPGA o...
Altera_ForumHonored Contributor
Honored ContributorI/O ports have large clock skew. For example, on an output port, the launch clock is the clock delay in the FPGA. Even on a global, it's 3-4ns pretty easily. The latch clock is a virtual clock that you create and has no physical delays in the FPGA, so its delay is 0ns. Hence your skew is whatever the launch clock delay is. The same is true for inputs except in reverese(latch clock has long delays and launch clock is virtual and 0ns). That is perfectly normal.
(May not apply to source synchronous constraints)
