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Altera_Forum
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14 years ago

negative clock skews

Hi guys, Having a negative clock skew at the output registers of around -5ns when working at 225Mhz. One reason maybe that i am not assigning the clock pin to a dedicated clock pin in FPGA o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Ok thanks for the reply..just one more question i tried using a dedicated clock pin...in my case there are [27:0]clkp and clkn i routed through them...this there anyodr pin which can be used as clk??