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Altera_Forum
Honored Contributor
Honored Contributornegative clock skews
Hi guys, Having a negative clock skew at the output registers of around -5ns when working at 225Mhz. One reason maybe that i am not assigning the clock pin to a dedicated clock pin in FPGA o...
Altera_ForumHonored Contributor
Honored ContributorNot using a dedicated clock pin is the likely cause.
General I/O pins can't drive the low skew global/clock networks. There isn't much guidance to give. You just need to choose one of the Dedicated Clock pins in the Pin Planner and assign the clock signal to it.
