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Altera_Forum
Honored Contributor
Honored ContributorNeed helps about SPI to I2S (an487)
Im trying to build a projest base on <SPI to I2S Using MAX II CPLDs> http://www.altera.com.cn/literature/an/an487.pdf
Im really confused about the WS bit of Command byte in the doc above. In the doc, saids, this WS bit specifies the word channel for each word of data that is received or transmitted. My understand is, the word channel bit set the I2S_WS bit, and I2S_WS should generated according to the CLK(input clock from a I2S slave device). so, this bit should be a readable only bit. or, it just means to synchronous the wrod channel whenever we sent a command? Many thanks, Shengkai Wu4 Replies
Altera_Forumok. i got it.
:) really appreciate for your help!!!!- Altera_Forum
You have to set it through SPI and toggle it at every word.
- Altera_Forum--- Quote Start --- In this application, the CPLD is always the master on the I2S bus. Therefore it generates both the I2S CLK and I2S WS signals for the slaves. The I2S WS signal takes its value from the WS control bit, and stays stable while the word is transmitted on the data line. --- Quote End --- thanks for your reply. Im agree that the CPLD is always the master on the I2S bus. My question is, does the WS control bit shift automatically or have to been set by SPI all the time?
- Altera_Forum
In this application, the CPLD is always the master on the I2S bus. Therefore it generates both the I2S CLK and I2S WS signals for the slaves. The I2S WS signal takes its value from the WS control bit, and stays stable while the word is transmitted on the data line.
