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Altera_Forum
Honored Contributor
Honored ContributorNeed helps about SPI to I2S (an487)
Im trying to build a projest base on <SPI to I2S Using MAX II CPLDs> http://www.altera.com.cn/literature/an/an487.pdf Im really confused about the WS bit of Command byte in the doc above. ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- In this application, the CPLD is always the master on the I2S bus. Therefore it generates both the I2S CLK and I2S WS signals for the slaves. The I2S WS signal takes its value from the WS control bit, and stays stable while the word is transmitted on the data line. --- Quote End --- thanks for your reply. Im agree that the CPLD is always the master on the I2S bus. My question is, does the WS control bit shift automatically or have to been set by SPI all the time?
