Altera_Forum
Honored Contributor
16 years agoneed help with some vhdl syntax
Hi, there:
I have been working with niosII for days. When I checked the vhd files that SOPC builder generated, I found some syntax that I had never encountered. They were: 1. a <= std_logic'(b); --a and b were defined as std_logic already 2. a <= std_logic_vector'(b); --a and b were defined as std_logic_vector already My first question is: Are they(std_logic'() and std_logic_vector'()) data type convertions? It really looks strange and seems unnecessary to put data type convertions there. But I think there must be a reason for it. What's that? Besides, how come there is an apostrophe(') coming with std_logic or std_logic_vector. It seems that std_logic() and std_logic_vector() are just ok. Best regards.