Need help to provide input/output timing constraint for DDR interface.

Hi All,

I am working on SD Card IP Core which has DDR interface.Input and Output Timing requirements is shown in the attached image.

where,tISUddr = 2.5ns,tIHddr = 2.5ns,tODLYddr_max = 7ns,tODLYddr_min = 1.5ns,tPP = 20ns

Timing constraint for Input/Ouput port are as given below.

//Clock Constraint

create_clock -name CLK -period 20ns [get_ports{CLK}]

//Input Delay Constraint

set_input_delay -clock { CLK } -max -add_delay $tODLYddr_max [get_ports {SD_DATA*}]

set_input_delay -clock { CLK } -min -add_delay -$tODLYddr_min [get_ports {SD_DATA*}]

set_input_delay -clock { CLK } -clock_fall -max -add_delay $tODLYddr_max [get_ports {sdhc_DAT*}]

set_input_delay -clock { CLK } -clock_fall -min -add_delay -$tODLYddr_min [get_ports {sdhc_DAT*}]

//Set False path between rising edge of CLK to falling edge of CLK

set_false_path -setup -rise_from [get_clocks {CLK}] -fall_to [get_clocks {CLK}]

set_false_path -setup -fall_from [get_clocks {CLK}] -rise_to [get_clocks {CLK}]

set_false_path -hold -fall_from [get_clocks {CLK}] -fall_to [get_clocks {CLK}]

set_false_path -hold -rise_from [get_clocks {CLK}] -rise_to [get_clocks {CLK}]

//Output Delay Constraint

set_input_delay -clock { CLK } -max -add_delay $tISUddr [get_ports {SD_DATA*}]

set_input_delay -clock { CLK } -min -add_delay -$tIHddr [get_ports {SD_DATA*}]

set_input_delay -clock { CLK } -clock_fall -max -add_delay $tISUddr [get_ports {sdhc_DAT*}]

set_input_delay -clock { CLK } -clock_fall -min -add_delay -$tIHddr [get_ports {sdhc_DAT*}]

//Set False path between rising edge of CLK to falling edge of CLK

set_false_path -setup -rise_from [get_clocks {CLK}] -fall_to [get_clocks {CLK}]

set_false_path -setup -fall_from [get_clocks {CLK}] -rise_to [get_clocks {CLK}]

set_false_path -hold -fall_from [get_clocks {CLK}] -fall_to [get_clocks {CLK}]

set_false_path -hold -rise_from [get_clocks {CLK}] -rise_to [get_clocks {CLK}]

//ALTDDIO BIDIR Megafunction Instance

alt_ddio_bidir inst

(

//DDIO Out Port

.outclock (CLK),

.datain_h (data_out_h),

.datain_l (data_out_l),

.oe (dir),

//DDIO In Port

.inclock (CLK),

.dataout_h (data_in_h),

.dataou_l (data_in_l)

);

Here CLK is used to generate data_out_h and data_out_l signals during write operation and the same CLK is used to capture

data_in_h and data_in_l signals.Same CLK is given to SD Card also.

Is these timing constraints are correct?

I refer DDR Timing Cookbook in which 16 different cases for DDR interface are explained.However in all those cases

center align clock or phase shifted clock is used to provide timing constraint.So is it possible to use same clock for

data launch and data latch?

Thanks in advance.