need help on state machine. Illegal character

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The screenshot is too small to see anything.

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thanks for reply

in the first picture show that condition from R1: Reset Wait to R0: Reset Start

reset with the condition " arbTimer >=resetDuration + RESET_WAIT " when I input the " + " in there, Quartus show another window which is send pic said " illegal verilog syntax found at character position 28, near + ".

How do I fix that problem?

So find the illegal Verilog syntax near position 28 and remove it.

Don't ask me what it is or on what line - only you have the Verilog code and my crystal ball is broken.

you need to convert expression like "arbTimer >=resetDuration + RESET_WAIT" to boolean equivalent like "cond_input = (arbTimer >=resetDuration + RESET_WAIT) "

and use cond_input in stateflow diagramm. I advise you to replace complex condition with simple one, and later in code you can insert how to calculate it .