New ContributorHi：
I use native phy to design SDI routine.
The data rate of Native PHY is 2970M and the data width is 20bit, and the simulation can be serialized normally.
However, after the data rate of Native PHY is 5940M and the data width is 40bit, it can't be serialized normally.
The simulation data is always 0, and signals such as pll lock and tx ready are normal.
All of the above use standard pcs.
Can you provide some ideas?
Thank you
Regular ContributorHello,
May I know which device are you using?
Regards,
Aqid
Regular ContributorIf you refer to the user guide, there is a mention in the note that supported FPGA fabric to PCS interface widths and the supported data rates are pending characterization.
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