Native PHY - Bitslip latency

Hi,

As I understand it, you have some inquiries related to the AV bit slip behavior in simulation. You seems to observe that there are ~ 10 clock cycle latencies from the bitslip assertion to the RX parallel data output change.

Based on my understanding on the AV XCVR channel PCS blocks, from word aligner (bitslip mode) to rx_parallel_data output, there are a number of PCS blocks ie rate match FIFO, 8b10b, byte deserializer, byte ordering and phase comp FIFO. Therefore, there will be latency from when you apply bitslip to when the data is observed at the rx_parallel_data output ports.

I believe the Figure 38. RX Bitslip in 16-bit Mode is just to show the high level concept of how bitslip would function.

Thus, I would recommend to refer to the functional simulation which would mimic the actual hardware behavior.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin