Mysterious trouble sharing FPGA RAM with HPS

Thanks; I did some unsuccessful digging: I found a library in the Quartus install called alt_cache.h but when I got it compiled, it threw an "illegal instruction" error. I the tried the built-in function __clear_cache() with no success.

I think had great success by using the Altera built-in IP megafunctions. I found that onchip_memory works just fine - an avalon bridge to the HPS works fine and controlling the RAM from the FPGA via an "External Bus to Avalon Bridge" had no "stale data" issues. I did not need even to use the volatile keyword in my code or try to clear the cache - it seems that these Altera modules deal properly with the cache. I hope this helps others with this problem. Please let me know if this is not clear or if I can be of further help.