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It looks like a problem with the data cache in the HPS. After writing to the RAM you should flush the data cache, and before reading it you should invalidate it. How are you running your software on the HPS? If it is barebone, there should be some cache management functions with the hardware lib provided by Altera.
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That sounds exactly like my problem - I had read about caches in processor design but it did not occur to me in this case. I'm not running 'bare metal'; I'm running the c-code through the Ubuntu linux that's part of the GHRD. I'm sorry for my ignorance, but some googling revealed several different ways to 'flush the data cache': cacheflush(char *s, int a, int b) as well as other, more platform-specific commands. It also looks like the cacheflush also invalidates the cache, but it's hard to be sure. What command would you suggest or where's a good place to look for more information?
Thank you for your quick reply!
Have a good weekend
Brian
Honored Contributor
