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Altera_Forum
Honored Contributor
Honored ContributorMy first experience with altera (MAX 10). And it didn't go well...
Hello everybody.
Finding the right FPGA can be quite a hassle. Especially when one search for a powerful one (read "lots of logic elements, DSP or memory stuff" for pure computing) with a few I/O using TQFP or similar package. In fact, nobody offers such products. So, it's all about compromises, except for package in my case. I first tried Lattice stuff with reasonable "little" FPGAs like the ECP2M line, the most powerful with these packages (even if there are in fact small). The 20K elements version could fit in the project I'm working for, but with no real margin. Xilinx have nothing better to offer. But Altera, with the MAX 10 series seems to be even more powerful with the TQFP 144 package (seems to me the only brand offering this kind of product). So, let's go for the MAX10 10M50SC. Simple, fast enough, versatile, "cheap" with some interesting stuff like DSP slices and, perhaps the integrated flash memory (the main marketing argument as far I can tell) but I don't care about this feature for the moment. How naive I was. Two days after digging into the awful documentation, where the obscure mixes with the obvious, I couldn't even know how I can program this thing. Even the very first stage of study is stuck with the lack of relevant information. The 64 pages document "MAX 10 FPGA Configuration User Guide" is a absolute reference of absence of any real usable information. Everything is mixed up; the vocabulary is obscure and it is only a list of what the device can do. Nothing about how to do these things or even understand the overall logic. When I read terms like "Remote System Upgrade" - perhaps my nonnative English origin mislead me - I think about a way to program the thing using for example a MCU, which is exactly what I wanted to do: sending a .sof file to the CRAM using the JTAG interface. Easy and straightforward, eh? In fact, we learn that we need a soft IP core or a "user interface" to do that. What is that? Why on earth I would need such a machinery to do what seemed to me a trivial task? So, I gave up this promising "Remote System Upgrade" which name is anything but what is seems to be. Now, after searching, reading, reading, searching for two days, I couldn't even find anything about programming the internal RAM of the chip. Of course, using Quartus and some programming tool does the business, it would be stupid and ridiculous to need exclusively such tools to upgrade this FPGA. Even the other manufacturers like Lattice provides the JTAG instructions and format. Even the smallest micro-controller like the 8051 has the full documentation and timing of the flash memory programming using the JTAG interface (it is just an example, check out the AN105 form silicon labs. That is what I call a relevant document). Now, I don't care about the flash memory in to FPGA. I only want to upload the CRAM image into the chip with my MPU. I have my flash memory for that with all the different firmwares. How simple and trivial could it be? For Altera, it seems irrelevant. Even finding how the destination of the image (CRAM or Flash) is chosen is impossible: nothing is said about choosing where the image is programmed except that it is stored in files with different extensions (.sof or .pof). Isn't this an important information? It seems not, because the programming tools knows - and it is the only thing that matters. Have to go to each customer with my laptop, a USB blaster and a license of Quartus, opening the box, plugging the JTAG and upgrade the Firmware? One must be joking. So, where is the pertinent information: the JTAG instructions for programming the device? Anyone ? Just an example of the madness of the documentation. Take a look at page 28 of this "MAX 10 FPGA Configuration User Guide". One can see the configuration sequence. Great. Seems clear. Now take a look page 34. This makes no sense at all. On one page, there is a sequence of states to apply to the nSTATUS, CONF_DONE and nCONFIG pins. On the other hand, they are connected as fixed pull-ups. It took me some time to understand that when they write "the xxxx pin is pulled low", they forgot to add "by the FPGA itself" (if I understand correctly – except that nCONFIG is an input… Whatever). This is so badly written that I'm very afraid about the rest. Have I to fight against the documentation to even try to start something? It's not specially an Altera/Intel specificity, I've had similar experience with Microchip or Lattice, but here a new level is reached. It seems to be normal. But I'm very irritated to spend the majority of my development time with external ridiculous causes instead of working on my own stuff. Other example that erodes the confidence about the documentation: the device pinouts. Any manufacturer offers package drawings with the pinouts. But it seems too old fashion or not "disruptive enough". Each device is described into an unreadable tableau (available on microfilms) with suspect stuff. Of course, there is no footprint or CAD data to integrate into the EDA software (except Cadence). It seems (as I could read somewhere in these forums) that it does not matter because one could create the component within minutes. Seems to me that these people never create libraries for these kind of component. Where is the VREFB1N0 pin (you know these common mode ouput voltage pins that are NOT explained at all in the handbook) in the 10M40 and 10M50 versions? Is it normal or is there a mistake there? I had to check with Quartus to be sure that, yes, this pin is NOT available in these versions. Why ? I don't know. But, you discover this by luck, like ton of other stuff. Isn't it an important detail ? Why there is no document showing all the differences with each versions of the MAX 10 line (not only the number of logic elements) ? These are only a few examples of crazy things I got during a few days of documentation reading, but I could add dozens of them. How one can choose so poorly documented parts? Only because it is Intel? Have I to choose a $30000 Stratix 10 to deserve good documentation? Or paying $$$ for technical support on trivial stuff? No, really, this didn't start well. And I still don't know how to program this thing. Jérôme.12 Replies
Altera_ForumI would respond you didn't read (or understand) what I've written :
The flash feature (that I've perfectly understood) does not interest me and is not the reason I've chosen the MAX10. The flash memory existence is irrelevant with the lack of documentation for programming the device. I can program the flash or the CRAM in a similar way, it doesn't matter. What are these apples and oranges I compare ? As I wrote twice, I don't use the Cyclone series because of the available packages (and it is much more expensive). Of course, I would choose this kind of chip if a TQFP version is available, do you think I'm this dumb !? You know, people can choose some stuff for reasons that are not what the marketing decided on the first place. And, to be honest, the MAX10 "specific feature" is risible, I don't see any real added value here. The MAX10 is much more specific (and interesting) because of its package related to the logic elements number than this dull flash feature. All I search for is a powerful enough FPGA with TQFP package. Only Altea (and perhaps Lattice) has something reasonable. I don't care about whistles and bells, only standard programming and reasonable documentation. Jerome.- Altera_Forum
Once more you're comparing apples and oranges and prove that you don't understand the specific features of MAX 10 family with internal flash configuration memory. It has been already suggested to use a "regular" cyclone FPGA with serial configuration interfaces if you want to configure it by an embedded processor.
Using JTAG interface through JAM STAPL player or a similar JTAG driver is possible, but surely not first choice. I'm out. - Altera_Forum
Hello everybody,
Thank you for this, perhaps there is a solution there. I don't mind adapting a JAM STAPL player source code into my MPU... if the source code is OK (the link seems to be very old stuff, late 90's at first glance). Can I have confidence with compatibility especially MAX10 ? I'm very reluctant to add additional hardware for some sort of "usb-blaster like" device, so why not ? In fact, I saw some stuff about STAPL but the documentation was so bad that I couldn't really understand what is it and what this involves. C source code is so much better. During my research, I didn't find this software section on the website. Just for "fun", I took a look at the Xinlinx Spartan 6 (I can not use it because of the packages) and the programming documentation. What a difference ! Everything is clear, well explained, SPI or JTAG, whatever. Time diagrams, definitions, schematics (both master ans slave situations). Xilinx doesn't no seems to consider the slave configuration (MPU programming the FPGA) as something alien as Altera seems to do... Even JTAG programming is perfectly described. Shame on you Altera ! I'll take a look at the JAM player idea. If I could get something usable, I would publish all source code and results on PIC32 implementation. I'm pretty sure it would interest some people. By the way, I could be perceived as a whinger, but I'm only French. Which could explain a lot. Jerome. - Altera_Forum
You could also try this:
http://dangerousprototypes.com/forum/viewtopic.php?f=56&t=3029 - Altera_Forum
Unfortunately the Max10 only has the JTAG to program it.
Have you seen this page: https://www.altera.com/support/support-resources/download/programming/jam.html It gives you the necessary source code. Of course now you can start complaining that the SPI (Lattice) or PS (Altera/Xilinx) is a lot simpler ... - Altera_Forum
Have you tried to speak directly to Altera via the mysupport portal?
- Altera_Forum
Hello everybody,
I installed Quartus a long time ago and I do perfectly know how to program this with a programmer. But, at the end, this device aims to be programmed by a MCU because, I have said, it would be stupid to force anybody to have a programmer and a specific hardware for firmware update, especially if there already exists such a mechanism for any MCU on the market (I program mine using a provided bootloader, an embedded http server and a dedicated flash memory). Why FPGA firmware would be once for all defined, especially for a hardware base that is planned to have future features once in the field ? Now, it is written in the reference document that the CRAM can be programmed directly. That's all I need. I can not believe that writing a simplified programmer only for this purpose is a difficult task. For me, it should be trivial - and I'm pretty sure it is : sending a block of data. If this device is IEEE1352 compliant, this is trivial if the manufacturer provides the instruction format and data. What I can see instead, is that it seems difficult to do a simple programmer because of the lack of documentation (and some sort of reverse engineering), not because it is a difficult task. It is very easy for any modern MCU, why it smells like hell in the FPGA world ? Is it so different ? I don't think so. It is only because the documentation is dire. The example of the application note of silicon labs illustrates this magnificently - and I'm 99.9% sure that the FPGA programming is as easy as programming this venerable 8051 MCU. I can not use Cyclone or other FPGA, as I said, because of the packages (and they are much more expensive !). The MAX 10 is the only "powerful enough" FPGA in TQFP package. Lattice have something similar but a little too limited. But, it is straightforward to program using SPI interface : it is documented. I'm sure that some people would say "get the IEEE1532 specifications and write your code !'". It is probably OK, but every single time I had to do this, the time needed to do something that working is absolutely enormous regarding to the actual needed time with the right documentation. Especially because these publications have a very obscure rhetoric style and are too general - they are not well suited for programming documentation. And, of course, I don't want to pay $125 for it. I've continued to search for information, and I had to read the BSDL files to get a little something (the supported IEEE1532 instructions). This was the only way to get something. I'm sorry, but this is ridiculous. In parallel, I took a look to new AVR MCU (I used to use Microchip). One datasheet. 1700 pages, everything inside. I found my old Intel Databooks from the early 90's. I used to use when I did x86 development and hardware. Thousands of pages with everything inside : pinouts, package drawing,time diagrams for everything, instruction set etc... And it was Intel ! Why Altera is so mediocre in this context (I didn't compare with Xilinx, but saying that the competitor is worse is an incredibly poor argument) ? But anyway, you get the point (at least I hope). Nobody tried to program an Altera FPGA with a MCU ? It seems to me incredible. And I'm sure that Altera has the right document somewhere, but where ? If Altera can not -or even worse doesn't want to- provide such generic document, that's it, I'll go for Lattice products. It's a shame because the MAX10 was ideal as a FPGA, but, at least, Lattice has some documentation. Jerome. - Altera_Forum
If you want to program the FPGA from a MCU, use a CycloneIV in stead of a MAX10 so you don't have to hassle with JTAG. The .rbf file is very easy to send across using the ps configuration mode (page 196 of the cyclone iv device handbook and following).
The MAX10 devices are at their best in true stand-alone deployment, where you use the Altera USB Blaster (or workalikes) to program the device once and then forget about them. - Altera_Forum
I think the original post should be about specific issues. I think the assumption that there are baby-steps per each device from start to end is not fair. And by just having decades of experience in another area related to electronic design doesn't mean you can do fpga overnight. Even ASIC engineers fall into this trap.
- Altera_Forum
The demeanor of your post doesn't particularly invite helpful answers, I'll try a few hints though.
You seem to stumble upon advanced features like Remote Upgrade before you read about the basic device usage. A blank MAX10 device need to receive it's initial configuration through JTAG interface, and probably 95 percent of MAX10 applications stay with this programming method. (@ TCWORLD: There's no AS programming for MAX10). A programming adapter directly supported by Quartus is the common way to use the JTAG interface, particularly in the lab. But basically any JTAG adapter or processor "talking" JTAG can configure the MAX10. Either storing a *.pof file in MAX10 flash or write a volatile *.sof image into MAX10 configuration memory. There are many ways to write data to or read it from MAX10 internal RAM. In most FPGA designs, you'll implement an interface protocol (e.g. SPI) to transfer the data. The RAM content is often initialized in the FPGA configuration, there are also debugging tools like the "In-system memory content editor" manipulating it through JTAG.
