Multipoint LVDS backplane Bus using Stratix IV GT

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I am planning to design a multi lane Multipoint LVDS full duplex Bus to connect multiple Stratix IV GT FPGAs across multiple boards through the backplane using in-built LVDS transceivers. Maximum receivers connected to a Tx line are 24. Could there be any Fanout issues here?.

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There are likely two issues you will face;

1. The LVDS buffers are not bidirectional, so you need to use both a transmitter LVDS pair, and a receiver LVDS pair. You can tie these together to make a potentially bidirectional LVDS signal, but

2. There is no tri-state control on the LVDS outputs, so you can not disable the transmitters without reconfiguring the FPGA.

This is the situation with the Stratix II FPGAs. I have not tested that this has changed on the Stratix IV, but I have not seen anything that indicates the LVDS design on the FPGAs has been changed.

You will not be able to implement full duplex using the LVDS on the FPGAs. If you absolutely have to implement this, since the backplane is already designed, you could use external LVDS transceivers from National Semiconductor and use FPGA single-ended I/O to communicate to the external LVDS transceiver.

Cheers,

Dave