Multiplexer Output Glitching

Thanks vjAlter, a search came up with the following which explains what I mean better than I managed:

http://www.alteraforum.com/forum/showpost.php?p=8506&postcount=7

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The LUT will be glitch-free only it is purposely designed so. E.g. the TpHL is longer than the TpLH so that a 'one' disappearing overlaps the next 'one' appearing. The simulations tend to go along that line.

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That will depend on the design of the LUT. If it is AND -> OR or OR -> AND may mean that TpHL needs to be shorter than TpLH (if I understand their meaning correctly). No matter the crucial bit is that the LUTs are glitch free if one and only one input changes.