Multiple High Speed ADCs via serial LVDS

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For multi-channels or multi-ADC chips, is it possible that the DCO do not need inside FPGA? Can we use internal same frequency clock as ADC data reference clock? So we can save one lvds channel.

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The shift between the supplied ADC clock and the resulting output DCO clock is not well specified making it (IMHO) impossible to set the exact capture point. So you need to use the DCO clock itself to sample the data streams.