multiple driver error during simulation

Hi

I am doing a project and am stuck in the synthesis part in Quartus.

The code was successfully compiled using icarus verilog software.But while compiling the code in Quartus , I get some error messages.

The code is as follows with its description:

/*

Whenever positive edge of switch occurs , I need to take the incoming 8 bits (serial inputs on a single pin) and after that I

have to discard all the bits, until the next posedge of switch. These bits are coming from a parallel in serial out register.

These bits are stored in a reg called c and i is an integer which keeps the count.

*/

module test(si,po,clk,switch,flag);

input si,clk,switch;

output reg [7:0] po;

reg [7:0] c,d;

output reg flag;

reg count;

//reg flag;

integer j,i;

initial i=0;

initial flag=0;

initial count=0;

always@(posedge clk)

begin

if (flag==1)

begin

c[i]=si;

i=i+1;

if(i==8)

begin

//count<=1;

//po<=c;

po<=(c[7:4]*10)+c[3:0];

i=0;

flag<=0;

end

end

end

always@(posedge switch)

begin

flag<=1;

end

endmodule

The error messges are as follows:

Error: Can't elaborate top-level user hierarchy

Error (10029): Constant driver at test.v(16)

Error (10028): Can't resolve multiple constant drivers for net "flag" at test.v(38)

Could anyone help in rectifying the mistake?