Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

multiple driver error during simulation

Hi I am doing a project and am stuck in the synthesis part in Quartus. The code was successfully compiled using icarus verilog software.But while compiling the code in Quartus , I get some error...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Well what I intend to do is that the serial bits are coming at every clock edge(global clock) . i use the switch mechanism to detect that my inputs are stable and I am ready to take the incoming 8 bits serially. So the value of count needs to be increased only when I am taking the inputs.

Hope this would clarify my specifications.