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Altera_Forum's avatar
Altera_Forum
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14 years ago

multiple driver error during simulation

Hi I am doing a project and am stuck in the synthesis part in Quartus. The code was successfully compiled using icarus verilog software.But while compiling the code in Quartus , I get some error...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I just corrected the output assignment.

Yes I detect switch rising level, the count is set to 1 due to one clock latency.

for safer design you may put this for edge detection:

if switch = '1' and switch_d = '0' then instead