Multiple Distinct Clocks Error

I suggested thinking in terms of how you want your logic implemented in physical resources like registers and register control signals. Then Rysc suggested doing that by thinking about how the logic looks in a schematic. Now that you have something you can synthesize, you can look at a post-synthesis schematic that represents what you did do. By comparing post-synthesis schematics to your HDL, you can see how the HDL was translated to physical device resources. This might help you next time to think in advance about how you want your logic to look as a schematic so that you can write the HDL in a style that produces what you want in hardware.

To see a direct correspondence between the HDL and an equivalent schematic representation of the logic as generic registers, muxes, AND gates, etc., use the RTL Viewer. To see the next step of how that logic maps into the device's registers, LUTs, RAM blocks, etc, use the Technology Map Viewer. Both of these schematic viewers are available at Tools --> Netlist Viewers.

Documentation on the schematic viewers is in the Quartus handbook, Volume 1, Section III, Chapter 12: Analyzing Designs with Quartus II Netlist Viewers.