Multiple Distinct Clocks Error

Before experimenting with the VHDL trying to fix it by trial and error:

For logic, think about what you want the hardware to look like in terms of registers versus combinational logic. For the register portion, you will have a D input, clock, asynchronous reset, and possibly other inputs like a clock enable. Write your VHDL in the recommended coding style for registers that have those input signals. For the coding styles, see the Quartus handbook, Volume 1, Section II, Chapter 6. In that chapter, see "Coding Guidelines for Registers and Latches".

For memory, go through a similar process to be clear about what you want for memory control signals like the clock. See "Inferring Memory Functions from HDL Code" in the same handbook chapter.