Multiple Distinct Clocks Error

You are right, you need the tick-event. That line means the clock has changed and it is nowt a '1'. Without the 'event, it just means when the clock is high, update this process, more like a transparent latch.

Before experimenting with the VHDL trying to fix it by trial and error:

Good referrences, and this gives me the forum to push my favorite book for people settling on a coding approach, HDL Chip Design by Doug Smith. He has, for example, all the typical flavors of a Flip Flop written with example code "The way it should be done" for both verilog and VHDL. There are little dialog boxes pointing to and explaining how each variation in the HDL text gives you a slightly different feature. It's not deep, but if you are looking for the right approach to basic synthesizable code, this is the ticket.

Thanks for the help. Pushing the signal assignments inside the if(clock'EVENT and clock='1') statement still generated the same error? I will read those links as well.

Get rid of the key(3)'EVENT and just use the value of key, as that will get rid of the error. You clk'EVENT already describes the clock for a register, and you can only have one clock for each register. Doug Smith's book should give you some good direction, although opening almost any VHDL file will show you the standard method for doing flops(Doug Smith's book will clarify what is going on). I think I mentioned this before, but I really think understanding schematics is a good way to start coding, even if you're writing VHDL/Verilog. If you're just starting coding, and can't imagine what the code you're writing would look like as a schematic, than you're in trouble. (The original code with multiple 'EVENT lines is a good example, is I don't know how to "draw" that.)

Thank you for everyone's help. I didn't really understand most of it, but I'll check out those references. Here is the way I finally solved the problem:

if(clock'EVENT and clock='1') then
			
			
			we <= '0';
			if(key(3)='1' and key(2)='1' and key(1)='1' and key(0)='1') then
				EnableKeyPress := '1';
			end if; 
			if(key(3)='0' and EnableKeyPress='1') then 
				EnableKeyPress := '0';
				if(conv_integer(ram_addr) = 16) then
					ram_addr <= "0000";
				else
				ram_addr <= ram_addr + "0001";
				end if;
			elsif(key(2)='0' and EnableKeyPress='1') then
				EnableKeyPress := '0';
				if(conv_integer(ram_addr) = 0) then
					ram_addr <= "1111";
				else
				ram_addr <= ram_addr - "0001";
				end if;
			elsif(key(1)='0' and EnableKeyPress='1') then 
				EnableKeyPress := '0';
				we <= '1';
				if(data_out = "11111111") then
					data_in <= "00000000";
				else
				data_in <= data_in + 1;
				end if;
			elsif(key(0)='0' and EnableKeyPress='1') then
				EnableKeyPress := '0';
				we <= '1';
				if(data_out = "00000000") then
					data_in <= "11111111";
				else
				data_in <= data_in - 1;
				end if;
			end if;
		end if;

I suggested thinking in terms of how you want your logic implemented in physical resources like registers and register control signals. Then Rysc suggested doing that by thinking about how the logic looks in a schematic. Now that you have something you can synthesize, you can look at a post-synthesis schematic that represents what you did do. By comparing post-synthesis schematics to your HDL, you can see how the HDL was translated to physical device resources. This might help you next time to think in advance about how you want your logic to look as a schematic so that you can write the HDL in a style that produces what you want in hardware.

Thank you. I will check out those references in the lab today after lunch.

"I didn't really understand most of it, but I'll check out those references."

I received the same error about the multiple clocks. My design had the following format:

process (rst, clk) begin
   if rising_edge(rst) then
      -- asynchronous reset stuff
   elsif rising_edge(clk) then
      -- synchronous stuff
   end if;
end process;

process (rst, clk) begin
   if (rst = '1') then
      -- asynchronous reset stuff
   elsif rising_edge(clk) then
      -- synchronous stuff
   end if;
end process;