Forum Discussion
Hi,
May I know if you have any updates?
Thanks
Best regards,
KhaiY
- fgh39825 years ago
New Contributor
Hello an thanks for following up on this discussion.
I use Quartus 9.0 in an old PC ant i try "classic timming analyser" and "Timequest timming analyser"
It's difficult to set up any clock node.
In my design i have 8 baseds clocks 33, 8, 4, ..... to 1 Mhz . Fmax are 33Mhz.
I have trouble to set up parameters for Quartus to take them into account .
After compiling , with classic timming i have this message :
Warning: Can't achieve minimum setup and hold requirement clk33 along 8752 path(s). See Report window for details .
I imagine this warning indicates that signals are not connected?clk33 are pin input clock clk0, my FPGA are ep3c10c8n. I use ~80% of cell and combinations fuctional and ~2500 logic registers
When i use timequest timming analyser there is apparently no error , is this normal in your opinion ?
Thank in advance.
Regards.
- corestar5 years ago
Contributor
>> I imagine this warning indicates that signals are not connected?
No, it probably means your "clocks" are not on global clock networks as @sstrell explained. The point of global and regional clocks is to provide a low-skew path to a large amount of logic.
>> When i use timequest timming analyser there is apparently no error , is this normal in your opinion ?
If you don't setup any constraints, you won't get any errors. Did you set the input clock frequency in your constraints. Also, you should put derive_pll_clocks in your .sdc file.I never understood why that was not the default, but without it the tools seem to assume the output clocks are the same frequency as the input clock.
Altera had some great free online training that would probably benefit you greatly. I think one was called something like "Becoming an FPGA Designer in 4 hours".
- fgh39825 years ago
New Contributor
Hello and Thank you for your reply.
Also i try Advisor function and timming optimisation advisor fuction.
It tell some settings, whet this setting are aplied it increase compiling time and it reduce the number of warnings
Regards.