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Honored Contributor
Honored ContributorMultipath timing constraints not giving expected results
Hi all, I am trying to constrain the timing for a design, where a part of the design resembles the included schematic. The paths which are failing timing are between two registers, where the...
Altera_ForumHonored Contributor
Honored Contributoryour mux is running on 2x rate (from diagram) so multicycle of 2 does not apply.
if you put one register on A before mux and on B before mux it might help timing
