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lambert_yu's avatar
lambert_yu
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2 years ago

multi-phase clock usage from the same one PLL

I have one question for multi-phase usage of PLL: In the LVDS IP usage, it has soft-cdr mode, and it could process >150Mbps serial siganl without following clock. But for the speed <150Mbps,...
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FvM's avatar
FvM
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2 years ago
Hi,
I would first think about using the provided SERDES DPA IP though, e.g. by twofold oversampling your input and adapting the design respectively.
If you want however to design multi-phase sampling on your own, you should study SERDES DPA respectively soft CDR topology. They essentially have the same problem you are facing and solved it.
lambert_yu's avatar
lambert_yu
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2 years ago

Hi, FvM

Thanks for your reply. Now this IP could only support the speed which is more than 150Mbps. The speed of our tx is 100Mbps, that means I need use 3 times sample rate compared to this speed. I don't know if there's enough toggle to make the soft-cdr work well. (But I will try this solution in out project. ) Based on this consideration, I try to design one soft-cdr which I need learn more knowledge about this technology.

BRs,

Lambert

  • FvM's avatar
    FvM
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    2 years ago

    Hi,
    if I understand right, the solution in SERDES IP is to drive the deserializer with actually selected vco_ph clock and perform domain crossing with parallel data. That's what I do in different kinds of soft CDR designs for FPGA series that don't provide hardware DPA (Cylone III to Cyclone 10, MAX 10).

    • lambert_yu's avatar
      lambert_yu
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      2 years ago

      Hi FvM,

      Thank you very much for providing this information.

      We will design one soft-cdr design based on the intel fpga. I expect there's opportunity to receive your guidance in the future. Any small help will be greatly appreciated.

      BRs,

      Lambert