multi-phase clock usage from the same one PLL

Hi Lambert,

I tried to discuss this issue with the expert and here is the feedback.

2. When synthesis the project, these clocks need to set constraints to keep the phase relationship?

All you need to do is define the reference clock in the .sdc file, and add the derive_pll_clocks constraint (method 2 in the link below), or use method 1. Quartus will know the timing relationships between all of the PLL output clocks and analyze appropriately.

https://www.intel.com/content/www/us/en/docs/programmable/683081/22-2/pll-clocks.html

3. If yes, how to set these constraints?

Refer to the above link.

5. Besides the above things, in order to achieve the goals, what should I notice?

a. If you do any clock muxing so you can select different phases for the data capture, then you should check out the Multi-Frequency Analysis section of the cookbook for the required constraints.

Regards,

Aqid