Contributor
Regular ContributorHi Lambert,
I found an application note that worth to look into.
Refer to this link: https://www.intel.com/content/www/us/en/docs/programmable/683845/current/i-o-pll-reconfiguration-and-dynamic.html
ContributorHi,
Glad to your response. But this file is for the dynamic phase adjust of the PLL. It's not same as my question.
My question is :
1. Configure the PLL output several same frequency clock with different phase after power on reset. (for example, 5 clocks and they are all 100Mhz. clock0 0 deg phase offset/ clock1 72deg phase offset/clock2 144deg phase offset/ clock3 216deg phase offset/clock4 288deg phase offset). That means PLL will output these clocks and the phase offset is fixed (do not need to dynamic configuration).
2. I will use these clocks to capture one same input, I could set the same delay from the input signal to the first flip-flop, meanwhile, I could set the same clock delay from the clock source to the first flip-flop; Then I could use clock0 to capture all five data samples.
2. When synthesis the project, these clock need to set constraints to keep the phase relationship?
3. If yes, how to set these constraints?
4. If no, it's better to use them directly.
5. Besides the above things, in order to achieve the goals, what should I notice?
BRs,
Lambert
