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Honored Contributormulti-channel source synchorous problem
my main board communicate with sevel sub-board ( up to 8 channel ) through lvds line ( one differencial clk and one differencial data ) using source synchorous. if i have 8 sub-board,then i must use 8 pair differencial clk and differencial data line.at receiver in my main-board ,I must use pll to generate high speed data sample clk from received low speed clk to sample data.but there are only 4 pll in my main-board fpga.How can i receive 8 channel data from sub-board ?
1 Reply
Altera_ForumYou don't say which FPGA's you are using at each end (main board and sub-boards) but if available, you could use use the DPA (Dynamic Phase Alignment) function of a SERDES but only if all comms is frequency locked to a single clock on the main board. That way, you would not even have to receive a clock from your sub-boards.
If the sub-boards are sending back comms data synchronized to local clocks then this won't work.
