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Altera_Forum
Honored Contributor
Honored ContributormSGDMA Transmission Data Missing
I am trying to transfer data using the mSGDMA QSYS cores in Quartus 17 from on-chip memory on an Arria V FPGA to a buffer allocated in Windows through PCIe and Jungo’s Windriver. Typically, the core ...
Altera_ForumHonored Contributor
Honored ContributorPart of the problem is that we are doing many hundred DMA transfers back to back and we never know when the bad data will show up. It makes it difficult to watch the Avalon MM bus when you cannot know which transfer will have the problem in it.
Any clue on what we could trigger on?
