mSGDMA stride reads/writes

That's correct, the write master will accept data even if it's not transfering. I meant to make this parameterizable so that you could prevent this from happening but I never got around to it. This feature is included for speed reasons since the DMA write data FIFO can be readied with data before the master beings transfering. One way to prevent this from happening would be to hack the RTL so that the Avalon-ST sink ready signal is gated by the !done (i.e. while the DMA is operating only then will data flow into the FIFO). If you wanted to see the fill level of the master you would need to add a conduit interface to the write master component and wire up the fill level to that conduit.

In order to read out the response you need to enable packet support in the write master. When that's enabled and the correct SOP and EOP bits are enabled in the descriptor the write master will keep track of how much data has been written and will report it to the dispatcher when the transfer is complete. This means that the IP providing the data will need to issue SOP on the first beat of streaming data and EOP on the last one.