Hi BadOmen,
I have another question:
I noticed that the Write-Masters do a Read-Ahead if my Fifos have data and there is no DMA-Transfer triggered.
This is no Problem for me, but is there a way to read out the Fill-Level of the Internal Fifo in the Master?
I was kind of confused when I wrote data to the Fifos and they suddenly disappeared (Fifo Fill-Level stayed 0).
But a DMA-Transfer with the right size gave me the data.
My problem is: I often don't know exactly how many data are received by the Fifos. If the disappear in the Write-Master I can only guess how many Bytes I have to transfer.
I tried the Response Registers of the msgdma-Core with Low-Level access via "pci_debug-Tool" (Linux), but all I got was a complete System-Breakdown and no "Actual Bytes Transferred" or "Error".
Can you help me?