mSGDMA stride reads/writes

Some common things I have heard of that help are:

1) Make sure you use the same burst size in the DMA as the PCIe core expects (it's either 64 or 32 depending on how you setup the PCIe core if I remember correctly)

2) Make sure the 'burst on aligned buffers' option in each master is disabled

3) Make sure you have multiple descriptors always queued up in the dispatcher to maintain a high throughput

When resetting the DMA you should monitor the reset status of the DMA since it doesn't stop on a dime because it has to wait for outstanding transactions to complete otherwise the fabric might lock up. So you should issue the reset, poll the DMA making sure the reset is complete, then take the DMA back out of reset. So what you might be seeing is a bunch of left over read data filling up the FIFO again after the reset is deasserted. Also you should be resetting the DMA dispatcher and masters by writing to the reset bit inside the dispatcher, if you are asserting the reset from outside the IP core through the reset inputs then you will most likely cause the DMA to violate the Avalon-MM spec (that reset should only be triggered if you are resetting the entire system).

Data in a FIFO should survive a reset because the memory cells cannot be cleared by a reset. The pointers and the fill levels get reset so the status from the FIFO will tell you it has been reset but valid data will be left behind. You shouldn't have to worry about that data being left behind becuase once you start filling the FIFO again they will get overwritten.