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Altera_Forum
Honored Contributor
11 years agoLook at the hps component interfaces (http://www.altera.com/literature/hb/cyclone-v/cv_54028.pdf) datasheet.
The AXI interface can be configured to 128-bit wide. Should you operate at 200MHz that's 3.2GBps. There'll be plenty of overhead that needs to be carried as part of this - bandwidth unavailable to you - but you should be able to carry what you need. You can find more details in the AXI Protocol Specification via the link in the document. You don't mention which Soc kit you're using. Altera's own has a user guide (http://www.altera.co.uk/literature/ug/ug_cv_soc_dev_kit.pdf) that references a Golden System Reference Design, that "demonstrates the hps features and the ability to communicate between hps to the fpga logic via the axi bridge interfaces." I'd suggest that's a good place to start. Regards, Alex