Altera_Forum
Honored Contributor
Honored Contributormore components in paths
hiii alll i am facing too many components in my critical path.. I know it depends on coding..but is there anything i can do in synthesis to reduce this total delay
Forum Discussion
Altera_ForumHonored Contributor
Honored ContributorNot sure. You might want to place with the state-machine encoding. (Binary is not necessarily faster, as it depends what states the output is dependent on. Quite often it is slower, but hard to tell until you try).
Enable Beneficial Skew shouldn't really gain 1ns. Note that there's a small delay in the LAB that can be on or off, and that's what this algorithm controls. Depends on device/speed grade, but I don't think it's more than a few hundred ps. But you may have gotten a different place and route? You mention 225MHz. Are you sure your constraints are correct? This is a general statement, but once you account for the external device delays, 225Mhz almost requires the FF in the IO cell. Again, it really depends on clock skew, clock constraints, etc. that isn't being shown. Just a concern.
