Forum Discussion
Altera_Forum
Honored Contributor
14 years agoYes RYSC tried your ideas...a bit of comparison of input and output slacks helped steal some time to the input..
Plus would like to add that using Enable Beneficial Skew Optimization provided me a help of 1ns and things came on track.. The hand placing of registers offcourse provided a help of 0.3 ns and would like to add that the path was fed to a state machine..do you kno how to optimize the logic of a state machine using binary encoding as seen in the rtl