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Altera_Forum
Honored Contributor
Honored Contributormore components in paths
hiii alll i am facing too many components in my critical path.. I know it depends on coding..but is there anything i can do in synthesis to reduce this total delay
Altera_ForumHonored Contributor
Honored ContributorIt's hard to say. First, I don't know by how much you fail timing. I also don't know what the clock looks like. The only major place for savings is that long IC, but it may be there to balance the delay to the output. You'd have to compare the input and output slacks and see if there is a way to steal from the output timing to help the input.
If you're not failing by much, it might be possible. If a PLL is feeding the register, you could phase-shift it forward a bit. You could also try hand-placing the register. Just some ideas, but it will be some work.
