Altera_Forum
Honored Contributor
Honored Contributormore components in paths
hiii alll i am facing too many components in my critical path.. I know it depends on coding..but is there anything i can do in synthesis to reduce this total delay
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Altera_ForumHonored Contributor
Honored ContributorOh thanks guys...And yes RYSC the inputs and outputs should be registered...
In this case as you can see the input is fed directly to a priority kinda logic around 4-5 mux...and the result is fed to a reg and den the output.. the constraint like fast input reg also fails because the input has not been registered.. Do you think the logic needs a change or it can be done with some synthesis constraints???
