Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Modling a State Machine in VHDL ... with trouble memorizing variables

Hi, I'm trying to make a state-machine wich remains in one of the states until one of the variables goes from zero to one three times. I assume it should be quite simple, but after some days I ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Apart from the "how to count" problem, you'll need at least two "counting" states that reflects a high respectively low input state. Then the transition to the counting_high state can also advance the counter. The counter would be incremented under rising_edge(clk).

Personally I prefer a more compact form of a state machine, that has only one, edge sensitive process. You can easily add things like the said counting action to it.