Modling a State Machine in VHDL ... with trouble memorizing variables

Thanks. I did not know I could not use it inside the combinational process. But - as far as I have seen - I can not do it either making a control like:

if (signal_to_monitor'event and signal_to_monitor='1') then accumulate<=accumulate+1 ;end if;

(I include a sample code at the end)

The intended behaviour I tried was just to 'stay in one state till the signal makes a number of changes (three in the example)'. It has no other application. So, I wanted to stay in the first state till the signal goes from 0 to 1. Then stay in second_st till 3 changes have been made in the signal (from 0 to 1). Once that happens (accumulate=3), return to first state and reset accumulate.

How can I do this? (the only solution is creating additional states like one_change, two_changes and three_changes? ) (if so, what if I needed 50 changes??? :( )

Thanks!

--

process (state,signal_to_monitor)

begin

next_state <= state;

if (signal_to_monitor'event and signal_to_monitor='1') then accumulate<=accumulate+1 ;end if;

case state is

when first_st =>

-- no ticks yet

if ( signal_to_monitor ='1') then

-- count one tick and go to the 'counting' state

next_state <= second_st;

else

accumulate <=0;

next_state <= first_st;

end if;

when second_st =>

-- if the signal goes to one again, count one more till you arrive to NUM_TICKS

-- then fall back to first_state

if (accumulate = NUM_TICKS) then

--

next_state<=first_st;

end if;

end case;