Modling a State Machine in VHDL ... with trouble memorizing variables

You can't place a counter in the combinational process. The output gets simply unpredictable this way. The accumulator must be assigned under control of an edge sensitive condition, similar to the state variable.

accumulate<=accumulate+1;

Also I don't see how the state machine can work with just two states.

I have difficulties to guess the exact intended behaviour. I suggest to sketch a waveform and use a different state for each step.

Care must be taken, if signal_to_monitor is unrelated to the system clock domain, e.g. an external signal. In this case, it's necessary to synchronize it by a clocked register and make the register output control the state machine.